Hallmark
A wireless split keyboard designed and built from scratch, including custom PCB, hand-soldered hardware, and firmware written in C on Zephyr RTOS with analog Hall Effect sensing and 1ms BLE.
Overview
Hallmark is a wireless 36-key split keyboard built from scratch: custom PCB, hand-soldered hardware, and firmware. Every key sits on an analog Hall Effect sensor, replacing the binary on/off of mechanical switches with full depth sensing. The firmware runs in C on Zephyr RTOS across dual nRF52840 MCUs, connected over BLE at a 1ms connection interval.
The Problem
Hall Effect keyboards with analog sensing exist, but only as full-size, proprietary, closed-source products. Split ergonomic boards use mechanical switches and miss every analog feature: rapid trigger, depth-based modifiers, per-key actuation tuning. There's nothing that combines both.
Design
- Sensing: A1304 linear Hall sensor per key, multiplexed through 3x CD74HC4051 per half. The nRF52840's 12-bit SAADC runs the full 18-key scan automated via PPI so the CPU sleeps through it.
- Firmware: C on Zephyr RTOS with Nordic's CAF for event-driven modules: rapid trigger with direction-reversal detection, depth-based home row mods, SOCD resolution, layered keymap, auto-calibration, and adaptive power management.
- Wireless: BLE Low Latency Packet Mode at 1ms connection intervals. Each half transmits raw analog positions to a XIAO nRF52840 dongle, which runs all input processing and outputs USB HID.
- Hardware: Custom KiCad PCB, hand-soldered SMD (SOT-23 sensors, SOIC-16 multiplexers), MX hotswap sockets, 750mAh LiPo per half, with a phased path from wired prototype to full wireless with CNC aluminum enclosure.
Highlights
- Analog depth per key enables rapid trigger at sub-0.2mm sensitivity, instant depth-based modifier activation, and firmware-adjustable actuation points
- Hardware-automated scan pipeline (timer -> GPIO mux select -> ADC sample -> DMA to RAM) keeps the CPU asleep during scans
- Open-source design with full documentation: system architecture, sensor specs, BOM, and a 6-stage hardware validation plan with quantitative pass/fail criteria